Espressif Systems /ESP32-S2 /UHCI0 /INT_ENA

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Interpret as INT_ENA

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RX_START_INT_ENA)RX_START_INT_ENA 0 (TX_START_INT_ENA)TX_START_INT_ENA 0 (RX_HUNG_INT_ENA)RX_HUNG_INT_ENA 0 (TX_HUNG_INT_ENA)TX_HUNG_INT_ENA 0 (IN_DONE_INT_ENA)IN_DONE_INT_ENA 0 (IN_SUC_EOF_INT_ENA)IN_SUC_EOF_INT_ENA 0 (IN_ERR_EOF_INT_ENA)IN_ERR_EOF_INT_ENA 0 (OUT_DONE_INT_ENA)OUT_DONE_INT_ENA 0 (OUT_EOF_INT_ENA)OUT_EOF_INT_ENA 0 (IN_DSCR_ERR_INT_ENA)IN_DSCR_ERR_INT_ENA 0 (OUT_DSCR_ERR_INT_ENA)OUT_DSCR_ERR_INT_ENA 0 (IN_DSCR_EMPTY_INT_ENA)IN_DSCR_EMPTY_INT_ENA 0 (OUTLINK_EOF_ERR_INT_ENA)OUTLINK_EOF_ERR_INT_ENA 0 (OUT_TOTAL_EOF_INT_ENA)OUT_TOTAL_EOF_INT_ENA 0 (SEND_S_REG_Q_INT_ENA)SEND_S_REG_Q_INT_ENA 0 (SEND_A_REG_Q_INT_ENA)SEND_A_REG_Q_INT_ENA 0 (DMA_INFIFO_FULL_WM_INT_ENA)DMA_INFIFO_FULL_WM_INT_ENA

Description

Interrupt enable bits

Fields

RX_START_INT_ENA

This is the interrupt enable bit for UHCI_RX_START_INT interrupt.

TX_START_INT_ENA

This is the interrupt enable bit for UHCI_TX_START_INT interrupt.

RX_HUNG_INT_ENA

This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt.

TX_HUNG_INT_ENA

This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt.

IN_DONE_INT_ENA

This is the interrupt enable bit for UHCI_IN_DONE_INT interrupt.

IN_SUC_EOF_INT_ENA

This is the interrupt enable bit for UHCI_IN_SUC_EOF_INT interrupt.

IN_ERR_EOF_INT_ENA

This is the interrupt enable bit for UHCI_IN_ERR_EOF_INT interrupt.

OUT_DONE_INT_ENA

This is the interrupt enable bit for UHCI_OUT_DONE_INT interrupt.

OUT_EOF_INT_ENA

This is the interrupt enable bit for UHCI_OUT_EOF_INT interrupt.

IN_DSCR_ERR_INT_ENA

This is the interrupt enable bit for UHCI_IN_DSCR_ERR_INT interrupt.

OUT_DSCR_ERR_INT_ENA

This is the interrupt enable bit for UHCI_OUT_DSCR_ERR_INT interrupt.

IN_DSCR_EMPTY_INT_ENA

This is the interrupt enable bit for UHCI_IN_DSCR_EMPTY_INT interrupt.

OUTLINK_EOF_ERR_INT_ENA

This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt.

OUT_TOTAL_EOF_INT_ENA

This is the interrupt enable bit for UHCI_OUT_TOTAL_EOF_INT interrupt.

SEND_S_REG_Q_INT_ENA

This is the interrupt enable bit for UHCI_SEND_S_REG_Q_INT interrupt.

SEND_A_REG_Q_INT_ENA

This is the interrupt enable bit for UHCI_SEND_A_REG_Q_INT interrupt.

DMA_INFIFO_FULL_WM_INT_ENA

This is the interrupt enable bit for UHCI_DMA_INFIFO_FULL_WM_INT interrupt.

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